The present invention relates to a semiconductor memory device and a process for producing the same. More particularly, the present invention relates to an improvement of a semiconductor memory device in which: MOS transistors are formed in a semiconductor substrate, are arranged in rows, and are isolated from each other by a plurality of field insulation films arranged in an island pattern; the MOS transistors aligned in one of said rows have one common gate which extends over one row of field insulation films; the MOS transistors aligned in one of said rows have a common first region for forming a drain or a source parallel to a plurality of the common gates; and a second region for forming another drain or source is surrounded by a pair of common gates and a pair of field insulation films, so that a plurality of the second regions are isolated from each other.
An example of the semiconductor memory device mentioned above is a programmable ROM (PROM). In the PROM, a number of MOS transistors are arranged in a silicon substrate and have a predetermined arrangement pattern, i.e., they are arranged in row form, as can be seen in a plan view of the PROM of FIG. 1. The gate may be of floating type electrodes, and information, i.e. either electrons or holes, is stored in them by causing an avalanche breakdown of the selected drains of the MOS transistors.
A mask ROM is one of the semiconductor memory devices mentioned above. Instead of the floating type gate, photomasks are utilized to write the information into the selected MOS transistors. In order to write the desired information into the selected MOS transistors by using the photomasks, electrode windows are formed through selected portions of an insulation layer or MOS transistors are selectively formed by means of the photomasks during the production of mask ROMs. In short, in the case of PROMs, the information can be electrically written by the user while in the case of mask ROMs, information can be written by the mask ROM producer with the aid of masks.
The conventional process of production of a PROM with a floating type gate is explained with reference to FIGS. 1 through 3.
In FIGS. 1 through 3, the field insulation films 2 of silicon dioxide are arranged on a P type silicon substrate 1 in an island pattern, as shown in FIG. 1. The drains 6 and sources 7 of the MOS transistors are formed by selectively diffusing N type impurities, such as phosphorus, into the P type silicon substrate 1. The drains 6 are partially exposed through the field insulation films 2 via through-holes 8 formed in the insulation layer, and aluminum conductors 9 (not shown in FIG. 1) are in contact with the drains 6. The gates 30 are formed on a gate oxide film 3 and consist of a polycrystalline silicon floating gate electrode 5, a polycrystalline silicon control gate electrode 5', and a silicon oxide film 4 located between the electrodes 5 and 5'. The polycrystalline silicon control gate electrodes 5' (indicated by the hatching in FIG. 1, upper right) extend laterally in FIG. 1, so that the MOS transistors aligned in either of the rows R.sub.1, R.sub.2, R.sub.3 or R.sub.4 have one common polycrystalline silicon control gate electrode 5'. Each common polycrystalline silicon control gate electrode 5' extends over the field insulation films 2 arranged in either of the rows R.sub.1, R.sub.2, R.sub.3 or R.sub.4. Each drain 6 is therefore surrounded by a pair of field insulation films 2 and a pair of gates 30, so that a plurality of drains 6 are isolated from each other. On the other hand, the MOS transistors aligned in either of the rows R.sub.1, R.sub.2, R.sub.3 or R.sub.4 have one common source 7.
For producing a PROM with floating type gate electrodes, as illustrated in FIGS. 1 through 3, field insulation films 2 are formed quickly on a P type silicon substrate 1 by oxidizing the substrate by means of the selective thermal oxidation method. The island pattern of the field insulation films 2 can be delineated by means of a well-known selective oxidation method. Subsequently, the gate oxide film 3 of each MOS transistor is formed by means of thermal oxidation. Then polycrystalline silicon floating gate electrodes 5 and polycrystalline silicon control gate electrodes 5', respectively, are formed by a chemical vapor deposition (CVD) method and the silicon oxide film 4 of each MOS transistor is formed by means of thermal oxidation. Phosphorus is then introduced into portions of the P type silicon substrate 1 exposed through the field insulation films 2 via apertures (not shown) by means of, for example, a diffusion method. In the formation of the gates 30, photoresist films (not shown) are used for successively delineating the polycrystalline silicon control gate electrodes 5', the silicon oxide films 4, and the polycrystalline silicon floating gate electrodes 5. Thus, the polycrystalline silicon control electrodes 5' extend entirely over the rows R.sub.1, R.sub.2, R.sub.3 and R.sub.4 while the polycrystalline silicon floating gate electrodes 5 (indicated by the hatching in FIG. 1, lower left) are located apart from each other in each of the rows R.sub.1, R.sub.2, R.sub.3 and R.sub.4. It is desirable from the point of view of producing highly integrated PROMs to decrease the dimensions of the PROM elements shown in FIGS. 1 through 3 and the distance between these elements. However, the distance l.sub.o between the gates 30 and the filed insulation films 2 cannot be decreased to less than approximately 1 micron, which is the smallest dimension or accuracy which can be achieved by means of the photolithographic technique. If the distance l.sub.o is decreased to less than approximately 1 micron, the result is that the electrical properties, for example the mutual conductance g.sub.m, of the transistors Tr.sub.1 and Tr.sub.2 will differ from one another due to an uncontrollable variation of distance l.sub.o. If the distance l.sub.o is designed to be less than 1 micron, the width of the polycrystalline silicon floating and control gate electrodes 5 and 5', respectively, on the field insulation films 2 will differ from that of the above-mentioned MOS transistors, especially the width of the central parts 5A of the polycrystalline silicon floating gate electrodes 5 and the polycrystalline silicon control gate electrodes 5', respectively (FIG. 1), due to the fact that the polycrystalline silicon floating gate electrodes 5 and the polycrystalline silicon control gate electrodes 5' are inevitably formed on the slope 2A (FIG. 3) or the inclined position of the field insulation films 2. Furthermore, there is a considerable difference in width between the delineation of the central parts 5A, and the delineation of the polycrystalline silicon floating gate electrodes 5 and the polycrystalline silicon control gate electrodes 5', respectively, to be formed on the slope 2A. The difference in width between the central parts 5A and the other parts of the polycrystalline silicon floating gate electrodes 5 and the polycrystalline silicon control gate electrodes 5' results in a disadvantageous difference between the electrical properties of the MOS transistors Tr.sub.1 and Tr.sub.2. In order to avoid such a disadvantage, the polycrystalline silicon floating gate electrodes 5 and the polycrystalline silicon control gate electrodes 5', have been conventionally formed on a flat part 2B of the field insulation films 2, as seen in the cross section along the line III--III'. In other words, the end (D) of each field insulation film 2, which faces one source 7 provided in common with the MOS transistors aligned in one of the rows R.sub.1, R.sub.2, R.sub.3 and R.sub.4, is disposed apart from the end of the respective common gate 30 and thus does not coincide with it. The distance l.sub.o determined in the light of not only the separation of the end D from the gate 30 but also the photolithographic accuracy can be as great as from 1.5 to 3 microns. Incidentally, the field insulation films 2 have such a function as to electrically isolate a selected MOS transistor(s) from an unselected MOS transistor(s). However, the part of the field insulation films 2 corresponding to the distance l.sub.o does not have a significant influence on the function of field insulation films 2 because a channel-cut layer (not shown) is usually formed beneath the field insulation films 2. Such a part of the field insulation films 2 is not necessary for the performance of PROMs; however, previously it was necessary for carrying out the photolithographic process.
The distances between various elements of PROMs and their dimensions are determined considering the accuracy of the photolithographic technique and the performance of PROMs. For example, the distance between the field insulation films 2 in a direction perpendicular to the gates 30 is usually 3 or 4 microns and is determined mainly in the light of the predetermined resistance of the sources 7 of PROMs.
The mask ROMs have the same disadvantages as do the PROMs when the mask ROMs are provided with gates, sources, drains and field insulations which have a plan geometric view or a plan view similar to that of the PROMs explained hereinabove. The cross-sectional structure of mask ROMs is different from that of PROMs. For example, the gate is not a floating type gate.